ISIG Executive Summit Taiwan 2026

Keynote Speaker

Navid Shahriari

Executive Vice President, Intel Foundry, Advanced Packaging Technology and Manufacturing Organization

Session info not yet published

Biography

Navid oversees large-scale teams developing some of the most complex packaging and substrate technologies and simultaneously delivering customer products from HVM worldwide sites. Bringing 35+ years of leadership and technical experience at Intel, across Products and Foundry, Navid has guided package assembly, embedded die packaging, substrates, test, validation, datacenter product portfolio, CPU core and GPU/NPU IP, ecosystem enablement, and silicon and packaging TD. He possesses a broad appreciation of customers’ needs at the intersection of design and build. Navid holds BS and Master of Technology degrees in Manufacturing Engineering from Arizona State University. He holds two patents and has authored technical papers and delivered keynote presentations across the industry.

Company Profile

Intel (Nasdaq: INTC) is an industry leader, creating world-changing technology that enables global progress and enriches lives. Inspired by Moore’s Law, we continuously work to advance the design and manufacturing of semiconductors to help address our customers’ greatest challenges. By embedding intelligence in the cloud, network, edge and every kind of computing device, we unleash the potential of data to transform business and society for the better.
To learn more about Intel’s innovations, go to newsroom.intel.com and intel.com.

Speaker

Dr. Raja Swaminathan

CVP, Advanced Packaging

Future of AI Hardware Enabled by Advanced Packaging

Day 1 / 11:55 - 12:15

Chiplet architectures are fundamental to the continued economic viable growth of power efficiency of AI hardware and edge computing. The slowing of Moore’s law has also placed advanced packaging at the critical juncture of technology-architecture intersection driving unique product capabilities. New heterogeneous architectures like 2.5D architectures and 3D Hybrid bonded architectures driving AMD’s industry leading advanced technology roadmap to enable power, performance, area, and cost (PPAC) will be discussed. Other topics including Chiplets for AI, challenges and solutions for large chiplet modules etc. will also be discussed.

Biography

Dr. Raja Swaminathan is the Corporate Vice President of Packaging at AMD, spearheading the development of AMD’s advanced packaging and heterogeneous integration roadmap. With a distinguished career spanning roles at Intel, Apple, and now AMD, Dr. Swaminathan’s expertise in design-technology co-optimization and dedication to optimizing power, performance, area, and cost (PPAC) have led to significant technological advancements such as EMIB, Apple’s Mx packages, 3D V-Cache, and 3.5D architectures for AI accelerators. Dr. Swaminathan holds a PhD from Carnegie Mellon University and an undergraduate degree from IIT Madras. With over 100 patents and more than 40 published papers to their name, Dr. Swaminathan was recently recognized as an IEEE Fellow and serves as a technical advisor to multiple startups. His unwavering commitment to heterogeneous integration continues to drive the boundaries of silicon technology.

Company Profile

For 50 years, AMD has driven in high-performance computing, graphics, and visualization technologies – the building blocks for gaming, immersive platforms, and the datacenter. Hundreds of millions of consumers, leading Fortune 500 businesses and cutting-edge scientific research facilities around the world rely on AMD technology daily to improve how they live, work and play. AMD employees around the world are focused on building great products that push the boundaries of what is possible. For more information about how AMD is enabling today and inspiring tomorrow, visit AMD (NASDAQ:AMD) on their website, blog, Facebook and Twitter pages.

Speaker

Dr. Philippe Absil

Vice President IC-Link | imec silicon solutions

Session info not yet published

Biography

At IC-Link / imec silicon solutions, Philippe Absil leads programs enabling custom ASIC design, prototyping, and advanced semiconductor integration. With over 20 years of experience in CMOS technology development and system design, Philippe has driven innovation in advanced nodes, 3D integration, and heterogeneous packaging. He holds a Ph.D. in Electrical Engineering and has authored numerous publications and patents in semiconductor process technology. At imec, Philippe focuses on bridging research and industry to accelerate time-to-market for next-generation chips in AI, automotive, and high-performance computing applications.

Company Profile

Imec is a world-leading research and innovation hub in advanced semiconductor technologies. Leveraging its state-of-the-art R&D infrastructure and the expertise of over 6,500 employees, imec drives innovation in semiconductor and system scaling, artificial intelligence, silicon photonics, connectivity, and sensing.
Imec’s advanced research powers breakthroughs across a wide range of industries, including computing, health, automotive, energy, infotainment, industry, agrifood, and security. Through IC-Link, imec guides companies through every step of the chip journey – from initial concept to full-scale manufacturing – delivering customized solutions tailored to meet the most advanced design and production needs.
Imec collaborates with global leaders across the semiconductor value chain, as well as with technology companies, start-ups, academia, and research institutions in Flanders and worldwide. Headquartered in Leuven, Belgium, imec has research facilities in Belgium, across Europe and the USA, and representation on three continents. In 2024, imec reported revenues of €1.034 billion.
Further information on imec can be found at www.imec-int.com.

Speaker

Sanjay Kumar

VP of PERLab

Session info not yet published

Biography

Sanjay is a Vice President of Kearney, former Senior Director at the U.S. CHIPS Program Office (Department of Commerce), where he led investment evaluations and negotiations for large-scale semiconductor manufacturing, packaging, and supply chain projects, contributing to nearly $30 billion in capital expenditures. With deep expertise in decision-making at the intersection of technology and policy, Sanjay has shaped critical initiatives within the semiconductor industry. Before his work in the public sector, he held leadership roles at companies including Meta, Intel, Broadcom, and NXP, where he spearheaded product development, corporate strategy, investments, and joint ventures. His extensive engagement with industry leaders across the high tec, automotive, and defense sectors has made him a trusted source of insights into technology trends and decision-making at the highest levels in public and private sector. Currently Sanjay is Vice president at Kearney, co-leading the PERL and semiconductor practice.

Company Profile

For 100 years, Kearney has been a leading management consulting firm and trusted partner to three-quarters of the Fortune Global 500 and governments around the world. With a presence across more than 40 countries, our people make us who we are. We work impact first, tackling your toughest challenges with original thinking and a commitment to making change happen together. By your side, we deliver—value, results, impact.

Speaker

John Tang

General Manager of AKMMV FCBGA

Session info not yet published

Biography

Long-term work in multinational companies and engage in ABF high-end substrate research and development, factory construction and large-scale production.With over twenty years of experience in the field of high-density ABF substrate for computer CPU chips, server chips, EMIB, glass and ceramic related to high-computing chips. In the past six years, he led the establishment of two intelligent factories dedicated to ABF substrate for Intel, guiding the company growing out of nothing, and being a leading factory in the global industry from weak in technology.Received the Intel Global Technology and Manufacturing Achievement Award. Granted 18 international patents and more than 20 articles and 4 Intel trade secrets.

Company Profile

AKMMV, is headquartered in Xiamen, with operations across Asia, Europe, and North America.
As a leader in China’s IC packaging substrate and high-end PCB sectors, we specialize in IC substrates, SLP, Any-layer HDI, Rigid-Flex, FPC, and power battery modules. We provide global customers with one-stop solutions ranging from R&D and design to precision manufacturing and SMT assembly.
Our global production network includes five domestic bases (Xiamen, Shanghai, Suzhou, Guangzhou, Fuzhou) and a facility in Thailand. By leveraging Digital Twins and AI, we have built smart factories that ensure full-process product traceability.Backed by over 870 patents and recognized as a “National Technological Innovation Demonstration Enterprise,” we maintain leadership in mSAP advanced processes and IC substrate technologies. We empower global giants in consumer electronics, automotive, and new energy sectors, driving advancements in 5G, intelligent driving, and high-end electronics.

We provide one-stop solution of highly raliable and advanced high density interconnects for global customers. and cover a wide range of products including substrates, substrates-like PCB, advanced & anylayer HDI, rigid-flex, flex and flex assembly, power battery module (CCS).

Speaker

Janet Tang

Partner & Managing Director

Disruption in Semiconductor Industry

Day 2 / 13:45 - 13:55

For over 40 years, AlixPartners has been helping clients confront disruption. Increasingly, cycles of disruption have displaced economic cycles as the primary business challenge.
Disruption is the new economic driver. We will share the results our 6th annual AlixPartners Disruption Index, with particular insights on how CEOs and senior executives of the semiconductor industry perceive major disruptions, opportunities and challenges in this exciting field around the globe.

Biography

Janet brings 20 years of a variety of industry experience such as as chief strategy officer (CSO) of a Global 500 company, oversight of P&L responsibilities, service in consulting leadership, role as a software architect, and engagements in entrepreneurship. Janet is known for successfully driving complex transformations in technology firms and telcos, turning around cost centers into profit centers, building transformative go-to-market engines, and coaching next generations of client leaders. Her early career as a software architect in Silicon Valley also gave her hands-on experience in R&D and product management.
Janet has a Master of Science in Computer Science from Stanford University. She has served as a board member of the University of Toronto Engineering Alumni Network and as chair of the network’s Nomination and Governance Committee.

Company Profile

AlixPartners is a results-driven global consulting firm that specializes in helping businesses respond quickly and decisively to their most critical challenges—from urgent performance improvement to complex restructuring, from risk mitigation to accelerated transformation. These are the moments when everything is on the line—a sudden shift in the market, an unexpected performance decline, a time-sensitive deal, a fork-in-the-road decision. We stand shoulder to shoulder with our clients until the job is done, and only measure our success in terms of the results we deliver.

Clients call us when they need pragmatism and cut-through to solve their most complex challenges arising from a continually disrupted world. Our services cover Artificial Intelligence, Corporate Strategy & Transformation, Data Governance, ESG, Growth, Investigations, Disputes & Advisory Services, Mergers & Acquisitions, Organizational Transformation, Supply-Chain Management & Operations, Technology, Transformative Leadership and Turnaround and Restructuring.

Speaker

Dr. Ami Eitan

SVP, Chief Scientific Officer

Session info not yet published

Biography

Ami Eitan received his B.Sc. in Chemical Engineering from Ben-Gurion University, Israel, his M.Sc. in Chemistry from the Weizmann Institute of Science, Israel, and his Ph.D. in Materials Science and Engineering from Rensselaer Polytechnic Institute, Troy, NY.
His work experience includes 16 years at Intel Corporation, as the head of the Technology Development of assembly interconnect department, 5 years as a director in the Advanced Packaging Technology and Service organization at TSMC, Taiwan, leading bonding technology development efforts, and now Ami is a SVP, Chief Scientific Officer at ASMPT SEMI solutions. Among his leading edge development programs, Ami led the Thermo-Compression Bonding technology development at Intel.
Ami’s areas of expertise include polymer-based composites, characterization of polymer systems, materials and process development for semiconductor packaging applications, TCB, HB, and other interconnect technology development.

Company Profile

ASMPT Limited, founded in 1975, is headquartered in Singapore and is listed in Hong Kong Stock Exchange since 1989.
ASMPT is the only company in the world that offers high-quality equipment for all major steps in the electronics manufacturing process – from carrier for chip interconnection to chip assembly and packaging to SMT. No other supplier offers a comparable range and depth of process expertise.
Semiconductor Solutions Segment Business of ASMPT offers a diverse product range from bonding to molding and trim & form to the integration of these activities into complete in-line systems for the microelectronics, semiconductor, camera modules, advanced packaging, photonics, and optoelectronics industries.
The group has successfully established itself as the leading player in the back-end assembly and packaging market with its innovative solutions and constant focus on customer value creation.

Speaker

Joshua Yoo

President

Static Control for Better Yield for AI & HPC Devices in Manufacturing

Day 1 / 17:00 - 17:10

Biography

Yong Hoon (Joshua) Yoo has been involved in the static control industry since 1994 for ionization, ESD measurement and ESD risk assessment service in semiconductor, flat panel displays and automotive industry. He has been a member of EOS/ESD Association since 2000 and served as an Elected Board of Director in 2016 – 2018. He is the founder and president of Korea EOS/ESD Association since 2011. He is a member of Institute of Electronics and Information Engineers (Korean IEEE) since 2021. He is serving industry as Korea President of International Semiconductor Executive Summits (ISES) since 2024.
He started his volunteering activities on EOS/ESD Association since 2013 as an active working group members, working group chair and technical program committee members of annual symposium for multiple events of ESD Association. With his leadership, Korea EOS/ESD Association very strongly presents and annual events over 10 years. He is a pioneer of contamination and ESD issue for flat panel display (FPD) in failure analysis and yield improvement. Since 2024, he conducted EOS/ESD assessment at multiple contract manufacturing sites and improved yield significantly in AI related chip and system manufacturing environment.
He is an iNARTE certified ESD Engineer in 2007 and the EOS/ESD Association certified Professional ESD Program Manager in 2011. He has 14 patents for ionization system and ESD testing technologies.

Company Profile

Core Insight, Inc. provides revolutionized ionization technology for EOS/ESD damage mitigation and yield improvement of AI related Advanced Package Device and HPC manufacturing environment in highly sophisticated and automated processes. Core Insight, Inc. provides Enhanced Process Assessment Services and case studies for Advanced Package Device and System Integration in manufacturing environment. Some company has increased their yield rate more than two digits of improvement and better deliverable.

Speaker

Hidenori Abe

Executive director, Electronics Business Headquarters and CTO for semiconductor materials

Session info not yet published

Biography

Hidenori Abe is CTO for semiconductor materials and Executive Director of Electronics Business Headquarters at Resonac. He leads R&D and strategy for electronic materials in semiconductors, substrates, and displays. Previously, Mr. Abe served as the head of the Electronics R&D Center and Packaging Solution Center, where he contributed to advanced packaging development through open innovation. Notably, in 2021, he directed the launch of JOINT2, a consortium targeting 2.xD and 3D packaging technologies. He received a master’s degree in chemical engineering from Tokyo Institute of Technology, Japan, and a master’s degree in the Executive MBA program from the University of Oxford, UK.

Company Profile

Resonac defines its purpose as “Change society through the power of chemistry.” Resonac aims to be a world-class functional chemical manufacturer, creating functions necessary for the times, supporting technological innovation, and contributing to the sustainable development of our customers. Resonac is Global Leading semiconductor materials supplier. In order to achieve technological innovation for solving various social issues, it is essential for us to make wide-ranging co-creative efforts with partners, and Resonac is open to collaboration including 1on1 co-development with any partner.
We have opened a Packaging Solution Center and are actively engaged in next-generation semiconductor co-creation activities through JOINT2 with many partner companies. Furthermore, starting this year, we will also seek co-creation opportunities in the United States by launching US-JOINT.

Speaker

Eric Lee

CEO

The Challenges of Heterogeneous Integration

Day 1 / 16:40 - 16:50

The Challenges in Heterogeneous Integration: Warpage, Singulation Defects, ESD/EOS/EMI, and Wet Process Issues
Heterogeneous integration (HI) combines multiple chip technologies within a single package, pushing the limits of materials, manufacturing, and reliability. Among the key challenges are warpage, singulation defects (such as Si chipping and cracking), electrostatic discharge (ESD), electrical overstress (EOS), electromagnetic interference (EMI), and issues related to wet process etching and cleaning.

Biography

Eric Lee is the CEO of Scientech Corp. and Chairman of Yayatech. He joined Scientech in 2004, following nearly a decade at UMC, where he held positions in both Taiwan and Singapore from 1995 to 2004.
In addition to his leadership roles at Scientech and Yayatech, Eric serves as President of the International Semiconductor Executive Summit (ISES) Taiwan. He is also a part-time professor in the Advanced Packaging Master’s Program at National Taiwan University of Science and Technology.
Eric contributes actively to the industry through his roles as a member of the SEMI Taiwan Advanced Packaging Committee and as a director of the Taiwan Electronic Equipment Industry Association.

Company Profile

Scientech Corporation was established in Taipei, Taiwan in 1979. We are a public company.
The industries we serve :
Semiconductor
Advanced Packaging
Compound semiconductor
Flat Panel Display
Micro LED
Scientific Instruments
High-tech related industries.
Business :
Wet Process Equipment & TBDB for Advanced Packaging like bumping, Fan-in, Fan-Out, 2.5D/3D IC
300mm Si Wafer Reclaim
Representative (Total solution with Equipment, Material, Components and Robot Repair)
Territory coverage :
Asia : Taiwan, China, Korea, Japan, SE Asia
USA
Europe
India
Welcome to contact us Info@scientech.com.tw

Speaker

Dr. Robert Wanninger

Senior Vice President Business Unit Advanced Backend Solutions

Session info not yet published

Biography

Robert Wanninger is Senior Vice President of the Advanced Backend Solutions (ABS) business unit at SUSS. With leading equipment and process solutions for Imaging, Coating and Bonding applications, SUSS ABS business unit is well positioned to serve the semiconductor industry.
Robert brings ~25 years of experience in semiconductor industry. Prior to joining SUSS in 2021, he has worked over 20 years at Infineon in various management positions and spent two years in Korea as COO of LS Power Semitech. He holds a PhD in Chemistry from the University of Regensburg, Germany.

Company Profile

SUSS is a leading supplier of equipment and process solutions for microstructuring in the semiconductor industry and related markets. In close cooperation with research institutes and industry partners SUSS contributes to the advancement of next-generation technologies such as 3D Integration and nanoimprint lithography as well as key processes for MEMS and LED manufacturing. With a global infrastructure for applications and service SUSS supports more than 8,000 installed systems worldwide. SUSS is headquartered in Garching near Munich, Germany. For more information, please visit suss.com.

The SUSS portfolio covers a comprehensive range of products and solutions for backend lithography, wafer bonding and photomask processing, complemented by micro-optical components. After sales, the company supports the entire life cycle of the tools: its range of services begins with the installation and startup of the systems including user training. Once systems are integrated in the customer’s environment, SUSS provides consistent support. Since long life cycles are very common for the company’s equipment, preventive maintenance programs are available, as well as reliable spare parts systems, warranty extensions and system upgrades. SUSS maintains service locations and local support teams in all areas of the globe to provide quick help.

Speaker

Dr. Pei-Lin Pai

CTO of Advanced Technology Development Group

Session info not yet published

Biography

Dr. Pei Lin PAI serves as the Chief Technology Officer of Winbond Electronics, overseeing strategic development in emerging memory, compute‑in‑memory architectures, and AI‑related technologies. He previously led multi‑generation DRAM, NOR, and ReRAM development as Vice President of Technology Development, and has held senior leadership roles at FocalTech and Nanya Technology, bringing extensive experience across semiconductor R&D, business development, and corporate strategy.

Company Profile

Winbond is a specialty memory IC company engaged in design, manufacturing and sales services. From product design, research and development, and wafer fabrication to the marketing of brand name products, Winbond endeavors to provide its global clientele top quality low to medium density memory solutions.

Panel Moderator

Dr. Kuan-Neng Chen

Dean/Chair Professor

Day 2 Morning Session Moderator

Day 2 / 08:38 -

Biography

Dr. Kuan-Neng Chen is Dean of International College of Semiconductor Technology and Chair Professor at Institute of Electronics at National Yang Ming Chiao Tung University (NYCU) in Taiwan. He received his Ph.D. degree in Electrical Engineering and Computer Science, as well as his M.S. degree in Materials Science and Engineering, both from Massachusetts Institute of Technology (MIT). Dr. Chen has held several prominent positions including Vice President for International Affairs, Associate Dean of International College of Semiconductor Technology at NYCU, Program Director of the Micro-Electronics Program at National Science and Technology Council in Taiwan, Adjunct R&D Director at Industrial Technology and Research Institute (ITRI), and Research Staff Member at IBM Thomas J. Watson Research Center.
Dr. Chen has received numerous awards and honors throughout his career, including IEEE EPS Exceptional Technical Achievement Award, IMAPS William D. Ashmon – John A. Wagnon Technical Achievement Award, National Industrial Innovation Award, MOST/NSTC Outstanding Research Award (twice), MOST/NSTC Futuristic Breakthrough Technology Award (twice), Pan Wen Yuan Foundation Outstanding Research Award, CIE Outstanding Professor Award, CIEE Outstanding Professor Award, and IBM Invention Achievement Awards (5 times). He has authored over 400 publications, including 3 books and 7 book chapters, and holds 88 patents. Dr. Chen served as Guest Editor for the MRS Bulletin, IEEE Transactions on Components, Packaging, and Manufacturing Technology, and Materials Science in Semiconductor Processing, and has held leadership roles in various conferences and committees, such as IEEE IITC General Chair. Dr. Chen is Fellow of National Academy of Inventors (NAI), IEEE, IET, IMAPS, and CIEE and member of Phi Tau Phi Scholastic Honor Society.
Additionally, Dr. Chen is Specially Appointed Professor at Institute of Tokyo Science (previously Tokyo Tech). His current research interests focus on three-dimensional integrated circuits (3D IC), advanced packaging, and heterogeneous integration.

Company Profile

3DIC Lab is led by Prof. Kuan-Neng Chen. The research topics include three-dimensional integrated circuits (3D IC), heterogeneous integration, and advanced packaging technology. As the scaling of transistor size faces its physical limits, 3D IC becomes the mainstream candidate to extend “Moore’s Law” and fulfill “More than Moore” applications. The vision is to demonstrate a highly prolific spirit of innovation in creating or facilitating outstanding inventions. The research goal is to make a tangible impact on the quality of life, economic development, and the welfare of society. The members firmly believe 3D IC is the key to leading semiconductor technology and electronic applications in the future innovation.
The research team and Prof. Kuan-Neng Chen have published more than 440 publications, including 3 books and 7 book chapters, and holds 91 patents. Attributed to our innovation and diligence, many of our significant research achievements have been published in IEDM, VLSI, and ISSCC. In addition to our outstanding academic achievements, 3DIC Lab has strong relationship with industries world-wide. Through the formats of joint development project (JDP) and non-exclusive technology transfer, 28 worldwide companies have benefited and further upgraded their technology and products. As a global leading research team in 3D IC field, 3DIC Lab collaborates world-wide universities, research institutes, and companies!

Panelist

Dr. Jeorge Hurtarte

Senior Director and Principal Marketing Strategist in the Compute Test Division

Session info not yet published

Biography

Dr. Jeorge Hurtarte is currently Senior Director and Principal Marketing Strategist in the Compute Test Division at Teradyne. Jeorge has held various technical, management and executive positions at Teradyne, Lam Research, LitePoint, TranSwitch, and Rockwell Semiconductors. Jeorge is on the Advisory Board of SEMI North America and serves as co-chair of the IEEE Heterogeneous Integration Roadmap (HIR) Test Chapter.
Jeorge holds a PhD in Electrical Engineering, and three master’s degrees (MBA, Computer Science, and Telecommunications). He is also visiting professor at the University of California, Santa Cruz and at the University of Phoenix. He is the co-author of the book Understanding Fabless IC Technology.

Company Profile

Teradyne designs, develops, and manufactures automated test equipment and advanced robotics systems. Its test solutions for semiconductors and electronics products enable Teradyne’s customers to consistently deliver on their quality standards. Its advanced robotics business includes collaborative robots and mobile robots that support manufacturing and warehouse operations for companies of all sizes.

Teradyne delivers manufacturing automation across industries, applications and the world. Teradyne solves complex test and automation challenges and enables businesses to achieve higher production volumes, higher quality and higher ROI. Teradyne designs, develops, and manufactures automatic test equipment used to test semiconductors, wireless products, data storage and complex electronics systems in a number of industries, including consumer electronics, wireless, automotive, industrial, computing, communications, and aerospace and defense. The industrial automation portfolio includes collaborative robotic arms, autonomous mobile robots (“AMRs”) and advanced robotic control software used by global manufacturing, logistics and industrial customers to improve quality, increase manufacturing and material handling efficiency, and decrease manufacturing and logistics costs. The automatic test equipment products include:
Semiconductor test systems
Storage and system-level test systems; Defense and aerospace test instrumentation and systems; Circuit-board test and inspection systems
Wireless test systems

Speaker

Onto Innovation

Session info not yet published

Biography

Company Profile

Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that include: Un-patterned wafer quality; 3D metrology spanning chip features from nanometer scale transistors to large die interconnects; macro defect inspection of wafers and packages; elemental layer composition; overlay metrology; factory analytics; and lithography for advanced semiconductor packaging. Our breadth of offerings across the entire semiconductor value chain helps our customers solve their most difficult yield, device performance, quality, and reliability issues. Onto Innovation strives to optimize customers’ critical path of progress by making them smarter, faster and more efficient. Headquartered in Wilmington, Massachusetts, Onto Innovation supports customers with a worldwide sales and service organization.
General Telephone: +1 978 253 6200
General email: info@ontoinnovation.com
Website: www.ontoinnovation.com

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ISIG Executive Summit Taiwan

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⭐⭐⭐⭐⭐ 5.0

ISIG Executive Summit Taiwan

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Speakers

Navid Shahriari

Executive Vice President, Intel Foundry, Advanced Packaging Technology and Manufacturing Organization

Dr. Raja Swaminathan

CVP, Advanced Packaging

Dr. Philippe Absil

Vice President IC-Link | imec silicon solutions

Sanjay Kumar

VP of PERLab

John Tang

General Manager of AKMMV FCBGA

Janet Tang

Partner & Managing Director

Dr. Ami Eitan

SVP, Chief Scientific Officer

Joshua Yoo

President

Hidenori Abe

Executive director, Electronics Business Headquarters and CTO for semiconductor materials

Eric Lee

CEO

Dr. Robert Wanninger

Senior Vice President Business Unit Advanced Backend Solutions